1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which comprises, for example, a floating gate.
2. Description of the Related Art
FIGS. 23 to 25 show a NAND-type EEPROM in which related-art shallow trench isolation (STI) is used. FIG. 23 is a plan view, FIG. 24 is a sectional view taken along line 24—24 of FIG. 23, and FIG. 25 is a sectional view taken along line 25—25 of FIG. 23. As shown in FIG. 24, a gate insulating film GI is formed as a tunnel insulating film on a silicon substrate, and a floating gate FG is formed on the film. The floating gate FG is cut between cells disposed adjacent to each other, and is electrically insulated. A structure for cutting the floating gate FG is referred to as a slit. The side walls and upper part of the floating gate FG in the slit are coated with an inter-gate insulating film IGI. When the floating gate FG is coated with the tunnel insulating film and inter-gate insulating film, it is possible to hold electric charges in the floating gate FG for a long period. Furthermore, a control gate CG is formed on the inter-gate insulating film. The control gate CG is usually shared by a large number of cell transistors, has a function of simultaneously driving a large number of cell transistors, and is represented as a word line WL.
On the other hand, a sectional direction shown in FIG. 25 is usually represented as a bit line BL direction. In the bit line BL direction, as shown in FIG. 25, stacked gate structures shown in FIG. 24 are arranged on the substrate. A resist or processing mask layer is used to process each cell transistor in a self-matching manner. In a NAND-type memory in which a plurality of cells are connected in series to one another via a selection gate, a source and drain are shared by the cells disposed adjacent to each other, and cell area is reduced. Moreover, an interval between the word lines WL is processed in a minimum dimension of fine processing.
A high write potential is applied to the control gate CG and the substrate is grounded to implant electrons into the floating gate FG. With miniaturization of the cell transistor, parasitic capacitances between the adjacent cells and between the floating gate FG and peripheral structure increase. Therefore, a write voltage of the cell transistor tends to increase in order to raise a write rate. To raise the write voltage, it is necessary to secure an insulating withstand voltage between the control gates CG and to raise a pressure resistance of a word line driving circuit. Therefore, this is a large problem in increasing a density/rate of a memory element.
The potential at the write time is roughly calculated from the structure of FIGS. 24 and 25. Capacitors which hold the gate insulating film and tunnel insulating film can be regarded between the control gate CG and floating gate FG and between the floating gate FG and substrate, respectively. Therefore, a memory cell seen from the control gate CG is equivalent to a structure in which two capacitors are connected to each other in series.
FIG. 26 shows an equivalent circuit in which a capacitor capacitance between the control gate CG and floating gate FG is Cip and a capacitor capacitance between the floating gate FG and substrate is Ctox. A potential Vfg of the floating gate FG at a time when a high potential for write (Vpgm=Vcg) is applied to the control gate CG is determined by a capacitive coupling between Cip and Ctox, and roughly calculated by the following equation:Vfg=Cr×(Vcg−Vt+Vt0); andCr=Cip/(Cip+Ctox),wherein Vt denotes a threshold voltage of the cell transistor, and Vt0 denotes a threshold voltage (neutral threshold voltage) in a case in which any electric charge is not applied through the floating gate FG.
When the potential Vfg of the floating gate FG is large, a high electric field is applied to the tunnel insulating film, and electrons are easily implanted into the floating gate FG. It is seen from the above equation that with Vcg set to be constant, a capacitance ratio Cr may be increased to enlarge Vfg. That is, Cip needs to be set to be large with respect to Ctox in order to reduce the write potential.
The capacitance of the capacitor is proportional to the permittivity of a thin film disposed between the electrodes and area of an opposed electrode, and inversely proportional to a distance between the electrodes disposed opposite to each other. A leakage current flows through the tunnel insulating film through which the electric charge is passed for write/erase, and the write/erase is inhibited. Therefore, a method of increasing a contact area of the gate insulating film with the floating gate FG, and control gate CG is usually used in order to increase Cip. For example, a slit width is reduced to enlarge the width (dimension 1a shown in FIG. 24) of the upper surface of the floating gate FG. Alternatively, a technique of increasing the film thickness of the floating gate FG to increase a length (dimension 1b shown in FIG. 24) of a side wall of the floating gate FG has been developed. However, as a result, it is necessary to excessively reduce a slit processed dimension as compared with a gate or wiring material. Moreover, when the film thickness of the floating gate FG is increased, it is increasingly difficult to process the gate. Furthermore, with the miniaturization, the parasitic capacitance between FG and FG disposed opposite to each other between the word lines WL increases. To maintain the capacitance ratio in this manner is a large factor for inhibiting the miniaturization of the cell transistor.
To solve the problem, there has been proposed a technique of changing the constitution of the floating gate FG or control gate CG to lower the write voltage.
For example, a NAND-type EEPROM has been developed in which the capacitance between a booster plate and floating gate is increased and which can perform a write/erase/read operation with a low voltage (e.g., Jpn. Pat. Appln. KOKAI Publication No 11-145429).
Moreover, a nonvolatile memory element has been developed in which a coupling ratio of the floating gate to the control gate is increased and the write voltage is reduced to miniaturize the element (e.g., Jpn. Pat. Appln. KOKAI Publication No 2002-217318).
Furthermore, a nonvolatile semiconductor memory device has been developed including MOSFET in which the floating gates are formed in opposite side walls of the control gate to enhance write/erase/read characteristic and which is a memory element (e.g., Jpn. Pat. Appln. KOKAI Publication No 2002-50703).
Additionally, an AG-AND memory cell has been developed in which an assist gate is disposed adjacent to the floating gate (e.g., 2002 IEEE, 952-IEDM, 21.6.1, 10-MB/s Multi-Level Programming of Gb-Scale Flash Memory Enabled by New AG-AND Cell Technology).
However, even by the above-described related art, it has been difficult to reduce the parasitic capacitance around the floating gate and to increase the capacitance between the control gate and floating gate. It has also been difficult to lower the write voltage and to achieve high integration and high rate.